Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression

Name: Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Author: Kakacak, Ahmet, Guzel, Aydın Emre, Cihangir, Ozan, Gören, S., Uğurdağ, Hasan Fatih

İsim	Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Yazar	Kakacak, Ahmet, Guzel, Aydın Emre, Cihangir, Ozan, Gören, S., Uğurdağ, Hasan Fatih
Basım Tarihi:	2017
Basım Yeri	- Elsevier
Konu	Fast multipliers, FPGA, Look-up table, Partial product generation, Column compression tree, Carry-save tree, Generalized parallel counter
Tür	Süreli Yayın
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	0167-9260
Kayıt Numarası	2540fd11-98a8-412f-9d7e-1011a39de784
Lokasyon	Electrical & Electronics Engineering
Tarih	2017
Örnek Metin	We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) unique as it automatically generates placement pragmas, (iv) uses a ternary adder as a final adder to exploit FPGA's internal carry-chains, and (v) employs a novel GPC based row compression, which aims to reduce the width of the final adder. We wrote Verilog generators for our method as well as one leading work in the literature. For synthesis, we wrote a script that can do “binary search” for the optimum latency. Our extensive implementation results on Xilinx Virtex-6 FPGAs show that we almost always produce circuits with smaller latency (i.e., timing) and Area-Timing Product (ATP) compared to the state-of-the-art in the literature, by 18% and 12% (on the average), respectively. We also offer smaller latency compared to the HDL * operator by 9% on the average at a cost of 12% larger ATP on the average. We are worse in latency in 6 cases out of 33, in all of which synthesis maps * to DSP slices. We also include area and energy results on Virtex-6 as well as a limited amount of latency, area, and ATP results on Virtex-5 and Altera Stratix III.
DOI	10.1016/j.vlsi.2016.12.012
Cilt	57

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Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression

Yazar Kakacak, Ahmet, Guzel, Aydın Emre, Cihangir, Ozan, Gören, S., Uğurdağ, Hasan Fatih

Basım Tarihi 2017

Basım Yeri - Elsevier

Konu Fast multipliers, FPGA, Look-up table, Partial product generation, Column compression tree, Carry-save tree, Generalized parallel counter

Tür Süreli Yayın

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 0167-9260

Kayıt Numarası 2540fd11-98a8-412f-9d7e-1011a39de784

Lokasyon Electrical & Electronics Engineering

Tarih 2017

Örnek Metin We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) unique as it automatically generates placement pragmas, (iv) uses a ternary adder as a final adder to exploit FPGA's internal carry-chains, and (v) employs a novel GPC based row compression, which aims to reduce the width of the final adder. We wrote Verilog generators for our method as well as one leading work in the literature. For synthesis, we wrote a script that can do “binary search” for the optimum latency. Our extensive implementation results on Xilinx Virtex-6 FPGAs show that we almost always produce circuits with smaller latency (i.e., timing) and Area-Timing Product (ATP) compared to the state-of-the-art in the literature, by 18% and 12% (on the average), respectively. We also offer smaller latency compared to the HDL * operator by 9% on the average at a cost of 12% larger ATP on the average. We are worse in latency in 6 cases out of 33, in all of which synthesis maps * to DSP slices. We also include area and energy results on Virtex-6 as well as a limited amount of latency, area, and ATP results on Virtex-5 and Altera Stratix III.

DOI 10.1016/j.vlsi.2016.12.012

Cilt 57