Author
Gören, S., Ozkurt, O., Yildiz, A., Uğurdağ, Hasan Fatih, Chakraborty, R. S., Mukhopadhyay, D.
Publication Date
2013-02
Publication Place
-
Elsevier
Subject
Field-Programmable Gate Arrays
Type
Periodical
Language
English
Digital
Yes
Manuscript
No
Library
Özyeğin University
Library Asset ID
0045-7906
Record ID
aa0dea4e-1472-4efc-b2f3-46de92f86fe4
Library Location
Electrical & Electronics Engineering
Date
2013-02
Notes
Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Sample Text
This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. With the aid of this technique, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Through DPSR, our PUF implementation does not steal real estate from the encrypted design. We also present a new DPSR flow for Xilinx FPGAs, which is difference-based but still allows modular design. It works regardless of the amount of difference between Partial Reconfiguration (PR) modules and is called DPSR-LD, where LD stands for Large-Difference. DPSR-LD is an enabler especially for Spartan-6 FPGA family, as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. Our DPSR-LD also includes a controller that interfaces to the ICAP and can process compressed bitstreams. It is called ICAP+ and occupies only 1% of Spartan-6 slices.
DOI
10.1016/j.compeleceng.2012.10.009
Cilt
39
