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Fast one- and two-pick fixed-priority selection and muxing circuits

Title	Fast one- and two-pick fixed-priority selection and muxing circuits
Author	Tosun, Mustafa, Özkan, M. Akif, Güzel, Aydin Emre, Uğurdağ, Hasan Fatih
Publication Date:	2016
Publication Place	- IEEE
Subject	Multi-pick priority encoder, Arbitration, Data selection, Computer arithmetic, Prefix graphs, Parameterized logic circuits, IP block
Type	Document
Language	English
Digital	Yes
Manuscript	No
Library:	Özyeğin University
Library Asset ID	978-1-5090-0693-9
Record ID	d68ab9ab-ab6f-45c4-a151-3d77b4fc2ea0
Library Location	Electrical & Electronics Engineering
Date	2016
Notes	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Sample Text	Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with circular data dependencies, the combined latency of the arbiter and muxing needs to be optimized. Moreover, there is an ever growing need for throughput. This requires switches that pick and multiplex more than one request per cycle. In this paper, we propose a family of circuit topologies where priority encoding picks one or two requests and takes place in parallel with muxing. We first present a scalable logic circuit for the 1-pick fixed-priority muxing problem and then extend it to the 2-pick problem. We compare the proposed architecture to its counterpart that does only priority encoding using Synopsis Design Compiler with ARM-Artisan TSMC 180 nm worst-case standard library. The results show that most of the priority encoding latency is hidden in the proposed circuit topology.
DOI	10.1109/EWDTS.2016.7807642

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Özyeğin University

Fast one- and two-pick fixed-priority selection and muxing circuits

Author Tosun, Mustafa, Özkan, M. Akif, Güzel, Aydin Emre, Uğurdağ, Hasan Fatih

Publication Date 2016

Publication Place - IEEE

Subject Multi-pick priority encoder, Arbitration, Data selection, Computer arithmetic, Prefix graphs, Parameterized logic circuits, IP block

Type Document

Language English

Digital Yes

Manuscript No

Library Özyeğin University

Library Asset ID 978-1-5090-0693-9

Record ID d68ab9ab-ab6f-45c4-a151-3d77b4fc2ea0

Library Location Electrical & Electronics Engineering

Date 2016

Notes Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Sample Text Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with circular data dependencies, the combined latency of the arbiter and muxing needs to be optimized. Moreover, there is an ever growing need for throughput. This requires switches that pick and multiplex more than one request per cycle. In this paper, we propose a family of circuit topologies where priority encoding picks one or two requests and takes place in parallel with muxing. We first present a scalable logic circuit for the 1-pick fixed-priority muxing problem and then extend it to the 2-pick problem. We compare the proposed architecture to its counterpart that does only priority encoding using Synopsis Design Compiler with ARM-Artisan TSMC 180 nm worst-case standard library. The results show that most of the priority encoding latency is hidden in the proposed circuit topology.

DOI 10.1109/EWDTS.2016.7807642