Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit
| Title | Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit |
|---|---|
| Author | Kurt, Alper |
| Publication Date: | 2021 |
| Publication Place | - IEEE |
| Type | Document |
| Language | English |
| Digital | Yes |
| Manuscript | No |
| Library: | Özyeğin University |
| Library Asset ID | 978-605011437-9 |
| Record ID | 0f348d1a-de86-4bad-9360-a493a3f03e96 |
| Date | 2021 |
| Sample Text | Pseudo Noise (PN) Sequences have been utilized for modern communication and measurement systems. They can be locally generated in both transmitters and receivers. PN sequence can be generated with Linear Feedback Shift Registers (LFSR). In this paper, LFSR based 4 bit and 8 bit PN sequence generator designs are proposed. Although PN sequence generator can be implemented on FPGA with VHDL, this paper focuses on the hardware implementation of PN sequence generator with Integrated Circuits (ICs) which can be found on the market to dispose of the cost of FPGA and design a PN sequence generator block which can be used for many systems. In the hardware implementation, if the initial seed of the LFSR is in all zero condition (0 0 0 0 for 4 bit) system would be locked and the PN sequence would never be generated. To overcome this problem, all zero condition protection circuit is proposed. |
| DOI | 10.23919/ELECO54474.2021.9677883 |
