Author
Yıldız, A., İskender, Deniz, Özlü, G., Uğurdağ, Hasan Fatih, Aktemur, Tankut Barış, Gören, S.
Publication Date
2019
Publication Place
-
IEEE
Subject
WCET, UART, CPU, Bit banging, FPGA, Proces-sor
Type
Document
Language
English
Digital
Yes
Manuscript
No
Library
Özyeğin University
Library Asset ID
978-172813964-7
Record ID
808cf177-dc9a-4711-9ff3-ac4dfceb8295
Library Location
Electrical & Electronics Engineering, Computer Science
Date
2019
Notes
TÜBİTAK
Sample Text
This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken by each function as output. A software UART system eliminates the need to employ a dedicated hardware for RS232 interface and makes directly use of the processor instead. For this purpose, we designed and implemented a memory-mapped system which has access to UART pins and is capable of setting and sampling these pins from software by a method of bit banging. We used the output of our WCET analyzer to approximate the actual bit times for a specific UART baud rate. By successfully testing and verifying our software UART, we showed that our WCET analyzer could be used to estimate runtime of tasks in an application. Although development of the WCET analyzer is ongoing, the results are promising.
DOI
10.1109/UBMK.2019.8907220
