Author
Gören, S., Özkurt, Ö., Türk, Y., Yıldız, A., Uğurdağ, Hasan Fatih
Publication Date
2013
Publication Place
-
IEEE
Subject
Field programmable gate arrays, Integrated circuit design, Modules
Type
Document
Language
English
Digital
Yes
Manuscript
No
Library
Özyeğin University
Library Asset ID
978-1-4799-3525-3
Record ID
ab0926ef-acfb-4994-adb3-e030a9b899c7
Library Location
Electrical & Electronics Engineering
Date
2013
Notes
Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Sample Text
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.
DOI
10.1109/IDT.2013.6727108
