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Generating fast logic circuits for m-select n-port round Robin arbitration

Title	Generating fast logic circuits for m-select n-port round Robin arbitration
Author	Uğurdağ, Hasan Fatih, Temizkan, F., Gören, S.
Publication Date:	2013
Publication Place	- IEEE
Subject	Adders, Logic circuits
Type	Document
Language	English
Digital	Yes
Manuscript	No
Library:	Özyeğin University
Library Asset ID	978-1-4799-0524-9
Record ID	4bf000d2-92c8-46d1-b7df-507d6b5de90c
Library Location	Electrical & Electronics Engineering
Date	2013
Notes	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Sample Text	This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our solutions, however, are based on parallel prefix networks, where the nodes are replaced by "saturated adder"s. We use mPE as a building block to construct an mRRA, which has single cycle latency and can arbitrate up to m requests per clock cycle. We took two arbiters from the liter rature, TC-PPA (1-select) and 3DP2S (2-select), and generalized them into mRRAs, which we call mTC-PPA and 3DPmS-RRA. We wrote fully parameterized HDL code generators. Logic synthesis results show that mTC-PPA and 3DPmS-RRA are up to 100% faster than the cascade solution and have up to 65% smaller Area-Timing Products (ATP). Comparing mTC-PPA and 3DPmS-RRA, 3DPmS-RRA circuits are slightly faster than mTC-PPA on the average. In terms of ATP, mTC-PPA is superior by far and can be as small as 30% of 3DPmS-RRA.
DOI	10.1109/VLSI-SoC.2013.6673286

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Özyeğin University

Generating fast logic circuits for m-select n-port round Robin arbitration

Author Uğurdağ, Hasan Fatih, Temizkan, F., Gören, S.

Publication Date 2013

Publication Place - IEEE

Subject Adders, Logic circuits

Type Document

Language English

Digital Yes

Manuscript No

Library Özyeğin University

Library Asset ID 978-1-4799-0524-9

Record ID 4bf000d2-92c8-46d1-b7df-507d6b5de90c

Library Location Electrical & Electronics Engineering

Date 2013

Notes Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Sample Text This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our solutions, however, are based on parallel prefix networks, where the nodes are replaced by "saturated adder"s. We use mPE as a building block to construct an mRRA, which has single cycle latency and can arbitrate up to m requests per clock cycle. We took two arbiters from the liter rature, TC-PPA (1-select) and 3DP2S (2-select), and generalized them into mRRAs, which we call mTC-PPA and 3DPmS-RRA. We wrote fully parameterized HDL code generators. Logic synthesis results show that mTC-PPA and 3DPmS-RRA are up to 100% faster than the cascade solution and have up to 65% smaller Area-Timing Products (ATP). Comparing mTC-PPA and 3DPmS-RRA, 3DPmS-RRA circuits are slightly faster than mTC-PPA on the average. In terms of ATP, mTC-PPA is superior by far and can be as small as 30% of 3DPmS-RRA.

DOI 10.1109/VLSI-SoC.2013.6673286