Yazar
Yüce, B., Uğurdağ, Hasan Fatih, Gören, S., Dündar, G.
Basım Tarihi
2014-08-01
Basım Yeri
-
IEEE
Konu
Computational complexity, Digital arithmetic, Hardware description languages, Network topology
Tür
Süreli Yayın
Dil
İngilizce
Dijital
Evet
Yazma
Hayır
Kütüphane
Özyeğin Üniversitesi
Demirbaş Numarası
0018-9340
Kayıt Numarası
7f274f0f-a4cc-4141-937f-d89fd2a61c8d
Lokasyon
Electrical & Electronics Engineering
Tarih
2014-08-01
Notlar
Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Örnek Metin
Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different (n, k) cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log n + log k), whereas the fastest in the literature is O(log n log k). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.
DOI
10.1109/TC.2014.2315634
Cilt
63
