Hardware division by small integer constants

Name: Hardware division by small integer constants
Author: Uğurdağ, Hasan Fatih, Dinechin, F. de, Gener, Y. S.

İsim	Hardware division by small integer constants
Yazar	Uğurdağ, Hasan Fatih, Dinechin, F. de, Gener, Y. S.
Basım Tarihi:	2017-12
Basım Yeri	- IEEE
Konu	Integer constant division, IP core generation, Parameterized HDL generator, Low latency combinational circuit, FPGA synthesis, ASIC synthesis
Tür	Süreli Yayın
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	0018-9340
Kayıt Numarası	9334f537-883b-481b-b44f-b3670288db81
Lokasyon	Electrical & Electronics Engineering
Tarih	2017-12
Notlar	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Örnek Metin	This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.
DOI	10.1109/TC.2017.2707488
Cilt	66

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Hardware division by small integer constants

Yazar Uğurdağ, Hasan Fatih, Dinechin, F. de, Gener, Y. S.

Basım Tarihi 2017-12

Basım Yeri - IEEE

Konu Integer constant division, IP core generation, Parameterized HDL generator, Low latency combinational circuit, FPGA synthesis, ASIC synthesis

Tür Süreli Yayın

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 0018-9340

Kayıt Numarası 9334f537-883b-481b-b44f-b3670288db81

Lokasyon Electrical & Electronics Engineering

Tarih 2017-12

Notlar Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Örnek Metin This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.

DOI 10.1109/TC.2017.2707488

Cilt 66