Synthesis of clock trees for sampled-data analog IC blocks

Name: Synthesis of clock trees for sampled-data analog IC blocks
Author: Yüce, B., Korkmaz, S., Esen, V. B., Temizkan, Fatih, Tunç, Cihan, Güner, Gökhan, Başkaya, I. F., Agi, İ., Dündar, G., Uğurdağ, Hasan Fatih

İsim	Synthesis of clock trees for sampled-data analog IC blocks
Yazar	Yüce, B., Korkmaz, S., Esen, V. B., Temizkan, Fatih, Tunç, Cihan, Güner, Gökhan, Başkaya, I. F., Agi, İ., Dündar, G., Uğurdağ, Hasan Fatih
Basım Tarihi:	2013
Basım Yeri	- IEEE
Konu	Analogue integrated circuits, Analogue-digital conversion, Electronic engineering computing, Integrated circuit design, Integrated circuit testing
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	978-1-4799-2095-2
Kayıt Numarası	e231180a-642b-4266-9e30-3aac97b8487a
Lokasyon	Electrical & Electronics Engineering
Tarih	2013
Notlar	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Örnek Metin	This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.
DOI	10.1109/EWDTS.2013.6673154

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Synthesis of clock trees for sampled-data analog IC blocks

Yazar Yüce, B., Korkmaz, S., Esen, V. B., Temizkan, Fatih, Tunç, Cihan, Güner, Gökhan, Başkaya, I. F., Agi, İ., Dündar, G., Uğurdağ, Hasan Fatih

Basım Tarihi 2013

Basım Yeri - IEEE

Konu Analogue integrated circuits, Analogue-digital conversion, Electronic engineering computing, Integrated circuit design, Integrated circuit testing

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 978-1-4799-2095-2

Kayıt Numarası e231180a-642b-4266-9e30-3aac97b8487a

Lokasyon Electrical & Electronics Engineering

Tarih 2013

Notlar Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Örnek Metin This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.

DOI 10.1109/EWDTS.2013.6673154