Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit

Name: Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit
Author: Kurt, Alper

İsim	Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit
Yazar	Kurt, Alper
Basım Tarihi:	2021
Basım Yeri	- IEEE
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	978-605011437-9
Kayıt Numarası	0f348d1a-de86-4bad-9360-a493a3f03e96
Tarih	2021
Örnek Metin	Pseudo Noise (PN) Sequences have been utilized for modern communication and measurement systems. They can be locally generated in both transmitters and receivers. PN sequence can be generated with Linear Feedback Shift Registers (LFSR). In this paper, LFSR based 4 bit and 8 bit PN sequence generator designs are proposed. Although PN sequence generator can be implemented on FPGA with VHDL, this paper focuses on the hardware implementation of PN sequence generator with Integrated Circuits (ICs) which can be found on the market to dispose of the cost of FPGA and design a PN sequence generator block which can be used for many systems. In the hardware implementation, if the initial seed of the LFSR is in all zero condition (0 0 0 0 for 4 bit) system would be locked and the PN sequence would never be generated. To overcome this problem, all zero condition protection circuit is proposed.
DOI	10.23919/ELECO54474.2021.9677883

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Design of 4 bit and 8 bit pseudo noise sequence generators with all zero condition protection circuit

Yazar Kurt, Alper

Basım Tarihi 2021

Basım Yeri - IEEE

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 978-605011437-9

Kayıt Numarası 0f348d1a-de86-4bad-9360-a493a3f03e96

Tarih 2021

Örnek Metin Pseudo Noise (PN) Sequences have been utilized for modern communication and measurement systems. They can be locally generated in both transmitters and receivers. PN sequence can be generated with Linear Feedback Shift Registers (LFSR). In this paper, LFSR based 4 bit and 8 bit PN sequence generator designs are proposed. Although PN sequence generator can be implemented on FPGA with VHDL, this paper focuses on the hardware implementation of PN sequence generator with Integrated Circuits (ICs) which can be found on the market to dispose of the cost of FPGA and design a PN sequence generator block which can be used for many systems. In the hardware implementation, if the initial seed of the LFSR is in all zero condition (0 0 0 0 for 4 bit) system would be locked and the PN sequence would never be generated. To overcome this problem, all zero condition protection circuit is proposed.

DOI 10.23919/ELECO54474.2021.9677883