Enabling difference-based dynamic partial self reconfiguration for large differences

Name: Enabling difference-based dynamic partial self reconfiguration for large differences
Author: Gören, S., Özkurt, Ö., Türk, Y., Yıldız, A., Uğurdağ, Hasan Fatih

İsim	Enabling difference-based dynamic partial self reconfiguration for large differences
Yazar	Gören, S., Özkurt, Ö., Türk, Y., Yıldız, A., Uğurdağ, Hasan Fatih
Basım Tarihi:	2013
Basım Yeri	- IEEE
Konu	Field programmable gate arrays, Integrated circuit design, Modules
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	978-1-4799-3525-3
Kayıt Numarası	ab0926ef-acfb-4994-adb3-e030a9b899c7
Lokasyon	Electrical & Electronics Engineering
Tarih	2013
Notlar	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Örnek Metin	This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.
DOI	10.1109/IDT.2013.6727108

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Enabling difference-based dynamic partial self reconfiguration for large differences

Yazar Gören, S., Özkurt, Ö., Türk, Y., Yıldız, A., Uğurdağ, Hasan Fatih

Basım Tarihi 2013

Basım Yeri - IEEE

Konu Field programmable gate arrays, Integrated circuit design, Modules

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 978-1-4799-3525-3

Kayıt Numarası ab0926ef-acfb-4994-adb3-e030a9b899c7

Lokasyon Electrical & Electronics Engineering

Tarih 2013

Notlar Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Örnek Metin This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.

DOI 10.1109/IDT.2013.6727108