Efficient combinational circuits for division by small integer constants

Name: Efficient combinational circuits for division by small integer constants
Author: Uğurdağ, Hasan Fatih, Bayram, A., Levent, Vecdi Levent, Gören, S.

İsim	Efficient combinational circuits for division by small integer constants
Yazar	Uğurdağ, Hasan Fatih, Bayram, A., Levent, Vecdi Levent, Gören, S.
Basım Tarihi:	2016
Basım Yeri	- IEEE
Konu	Integer constant division, Parameterized circuit generator, RTL generator, Low latency combinational circuit, Area-time product, ASIC synthesis
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	1063-6889
Kayıt Numarası	08d64bcc-5d75-4907-b1f8-1f29d4bb3978
Lokasyon	Electrical & Electronics Engineering
Tarih	2016
Örnek Metin	Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of this problem, where the divisor is small and the circuit outputs a quotient and remainder. We propose a fast (low-latency) yet area-efficient combinational circuit topology, which we call Binary Tree based Constant Division (BTCD). BTCD uses a collection of small LUTs wired to each other to form a binary tree. The circuit also has bunch of adders, whose latencies are almost hidden as they operate in parallel with the binary tree. We wrote RTL code generators for BTCD and two previous works in the literature, then generated circuits for dividends of up to 128 bits and divisors of 3, 5, 11, and 23. We synthesized the generated RTL designs using a commercial ASIC synthesis tool. BTCD strikes a good balance between timing (latency) and area. It is up to 3.3 times better in Area-Timing Product (ATP) compared to the best alternative. ATP has a good correlation with energy consumption.
DOI	10.1109/ARITH.2016.23

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Efficient combinational circuits for division by small integer constants

Yazar Uğurdağ, Hasan Fatih, Bayram, A., Levent, Vecdi Levent, Gören, S.

Basım Tarihi 2016

Basım Yeri - IEEE

Konu Integer constant division, Parameterized circuit generator, RTL generator, Low latency combinational circuit, Area-time product, ASIC synthesis

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 1063-6889

Kayıt Numarası 08d64bcc-5d75-4907-b1f8-1f29d4bb3978

Lokasyon Electrical & Electronics Engineering

Tarih 2016

Örnek Metin Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of this problem, where the divisor is small and the circuit outputs a quotient and remainder. We propose a fast (low-latency) yet area-efficient combinational circuit topology, which we call Binary Tree based Constant Division (BTCD). BTCD uses a collection of small LUTs wired to each other to form a binary tree. The circuit also has bunch of adders, whose latencies are almost hidden as they operate in parallel with the binary tree. We wrote RTL code generators for BTCD and two previous works in the literature, then generated circuits for dividends of up to 128 bits and divisors of 3, 5, 11, and 23. We synthesized the generated RTL designs using a commercial ASIC synthesis tool. BTCD strikes a good balance between timing (latency) and area. It is up to 3.3 times better in Area-Timing Product (ATP) compared to the best alternative. ATP has a good correlation with energy consumption.

DOI 10.1109/ARITH.2016.23