Output domain downscaler

Name: Output domain downscaler
Author: Büyükmıhçı, M., Levent, Vecdi Emre, Guzel, Aydın Emre, Ates, Ozgur, Tosun, Mustafa, Akgün, T., Erbas, C., Gören, S., Uğurdağ, Hasan Fatih

İsim	Output domain downscaler
Yazar	Büyükmıhçı, M., Levent, Vecdi Emre, Guzel, Aydın Emre, Ates, Ozgur, Tosun, Mustafa, Akgün, T., Erbas, C., Gören, S., Uğurdağ, Hasan Fatih
Basım Tarihi:	2016
Basım Yeri	- ISCIS 2016: Computer and Information Sciences
Konu	Image interpolation
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	1865-0929
Kayıt Numarası	4b2ee82c-3665-43d4-bb6e-2d5e4a571af7
Lokasyon	Electrical & Electronics Engineering
Tarih	2016
Notlar	Artemis ; TÜBİTAK
Örnek Metin	This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with Edge Detection and Sharpening Spatial Filter. We compare ODD to a straight-forward implementation of the same combination of methods, which we call Input Domain Downscaler (IDD). IDD tries to output a new pixel of the downscaled video frame every time a new pixel of the original video frame is received. However, every once in a while, there is no downscaled pixel to produce, and hence, IDD stalls. IDD sometimes also skips a complete row of input pixels. ODD, on the other hand, spreads out the job of producing downscaled pixels almost uniformly over a frame. As a result, ODD is able to employ more resource sharing, i.e., can do the same job with fewer arithmetic units, thus offers a more area-efficient solution than IDD. In this paper, we explain how ODD and IDD work and also share their FPGA synthesis results.
DOI	10.1007/978-3-319-47217-1_28
Cilt	659

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Output domain downscaler

Yazar Büyükmıhçı, M., Levent, Vecdi Emre, Guzel, Aydın Emre, Ates, Ozgur, Tosun, Mustafa, Akgün, T., Erbas, C., Gören, S., Uğurdağ, Hasan Fatih

Basım Tarihi 2016

Basım Yeri - ISCIS 2016: Computer and Information Sciences

Konu Image interpolation

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 1865-0929

Kayıt Numarası 4b2ee82c-3665-43d4-bb6e-2d5e4a571af7

Lokasyon Electrical & Electronics Engineering

Tarih 2016

Notlar Artemis ; TÜBİTAK

Örnek Metin This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with Edge Detection and Sharpening Spatial Filter. We compare ODD to a straight-forward implementation of the same combination of methods, which we call Input Domain Downscaler (IDD). IDD tries to output a new pixel of the downscaled video frame every time a new pixel of the original video frame is received. However, every once in a while, there is no downscaled pixel to produce, and hence, IDD stalls. IDD sometimes also skips a complete row of input pixels. ODD, on the other hand, spreads out the job of producing downscaled pixels almost uniformly over a frame. As a result, ODD is able to employ more resource sharing, i.e., can do the same job with fewer arithmetic units, thus offers a more area-efficient solution than IDD. In this paper, we explain how ODD and IDD work and also share their FPGA synthesis results.

DOI 10.1007/978-3-319-47217-1_28

Cilt 659