RoCoCo: row and column compression for high-performance multiplication on FPGAs

Name: RoCoCo: row and column compression for high-performance multiplication on FPGAs
Author: Uğurdağ, Hasan Fatih, Keskin, O., Tunç, Cihan, Temizkan, Fatih, Fici, G., Dedeoğlu, S.

İsim	RoCoCo: row and column compression for high-performance multiplication on FPGAs
Yazar	Uğurdağ, Hasan Fatih, Keskin, O., Tunç, Cihan, Temizkan, Fatih, Fici, G., Dedeoğlu, S.
Basım Tarihi:	2011
Basım Yeri	- IEEE
Konu	Adders, Application specific integrated circuits, Field programmable gate arrays, Integrated circuit design
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	978-1-4577-1957-8
Kayıt Numarası	e0ce54da-8e36-4478-afb6-1b06bb20e1de
Lokasyon	Electrical & Electronics Engineering
Tarih	2011
Notlar	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Örnek Metin	Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.
DOI	10.1109/EWDTS.2011.6116419

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RoCoCo: row and column compression for high-performance multiplication on FPGAs

Yazar Uğurdağ, Hasan Fatih, Keskin, O., Tunç, Cihan, Temizkan, Fatih, Fici, G., Dedeoğlu, S.

Basım Tarihi 2011

Basım Yeri - IEEE

Konu Adders, Application specific integrated circuits, Field programmable gate arrays, Integrated circuit design

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 978-1-4577-1957-8

Kayıt Numarası e0ce54da-8e36-4478-afb6-1b06bb20e1de

Lokasyon Electrical & Electronics Engineering

Tarih 2011

Notlar Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Örnek Metin Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.

DOI 10.1109/EWDTS.2011.6116419