FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication

Name: FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication
Author: Annafıanto, Nur Fajar Rızqı, Jabir, M. V., Burenkov, I. A., Uğurdağ, Hasan Fatih, Battou, A., Polyakov, S. V.

İsim	FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication
Yazar	Annafıanto, Nur Fajar Rızqı, Jabir, M. V., Burenkov, I. A., Uğurdağ, Hasan Fatih, Battou, A., Polyakov, S. V.
Basım Tarihi:	2020-09
Basım Yeri	- IEEE
Konu	FPGA, CORDIC, DDS, SFDR, Pipeline, Latency
Tür	Belge
Dil	İngilizce
Dijital	Evet
Yazma	Hayır
Kütüphane:	Özyeğin Üniversitesi
Demirbaş Numarası	978-172819899-6
Kayıt Numarası	287fdb39-4744-4387-9079-93f2fda89a78
Lokasyon	Electrical & Electronics Engineering
Tarih	2020-09
Notlar	Foundation USA
Örnek Metin	A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to look-up-based methods and low latency. The latency depends on the number of iterations, which is determined by the number of angles in the rotation set. However, it is necessary to maintain high spectral purity to optimize the overall system performance. To optimize the opportunity of quantum measurement, low latency and a high spectral purity sine wave generator is essential. The implementation of this design generates output with 64% latency reduction compared to that of the conventional CORDIC design and 72.2 dB SFDR value.
DOI	10.1109/EWDTS50664.2020.9225029

Kaynağa git Özyeğin Üniversitesi

Aramaya Dön

Özyeğin Üniversitesi

Kaynağa git

FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication

Yazar Annafıanto, Nur Fajar Rızqı, Jabir, M. V., Burenkov, I. A., Uğurdağ, Hasan Fatih, Battou, A., Polyakov, S. V.

Basım Tarihi 2020-09

Basım Yeri - IEEE

Konu FPGA, CORDIC, DDS, SFDR, Pipeline, Latency

Tür Belge

Dil İngilizce

Dijital Evet

Yazma Hayır

Kütüphane Özyeğin Üniversitesi

Demirbaş Numarası 978-172819899-6

Kayıt Numarası 287fdb39-4744-4387-9079-93f2fda89a78

Lokasyon Electrical & Electronics Engineering

Tarih 2020-09

Notlar Foundation USA

Örnek Metin A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to look-up-based methods and low latency. The latency depends on the number of iterations, which is determined by the number of angles in the rotation set. However, it is necessary to maintain high spectral purity to optimize the overall system performance. To optimize the opportunity of quantum measurement, low latency and a high spectral purity sine wave generator is essential. The implementation of this design generates output with 64% latency reduction compared to that of the conventional CORDIC design and 72.2 dB SFDR value.

DOI 10.1109/EWDTS50664.2020.9225029