Back to Search

Using high-level synthesis for rapid design of video processing pipes

Title	Using high-level synthesis for rapid design of video processing pipes
Author	Güzel, Aydin Emre, Levent, Vecdi Emre, Tosun, Mustafa, Özkan, M. Akif, Akgun, T., Büyükaydın, D., Erbas, C., Uğurdağ, Hasan Fatih
Publication Date:	2016
Publication Place	- IEEE
Subject	High-level synthesis, Vivado HLS, Video processing pipelines, Optical flow
Type	Document
Language	English
Digital	Yes
Manuscript	No
Library:	Özyeğin University
Library Asset ID	978-1-5090-0693-9
Record ID	a6a8d24e-1735-40fb-b778-03bf3069b9e6
Library Location	Electrical & Electronics Engineering
Date	2016
Notes	Due to copyright restrictions, the access to the full text of this article is only available via subscription.
Sample Text	In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has turned out to be pretty general-purpose except for the ability to handle cyclic inter-iteration dependencies. It also introduces some novel concepts to HLS, such as “pipelined multiplexers”. The synthesis results show that we can achieve better timing or better area results compared to Vivado HLS. Furthermore, the Verilog RTL our HLS tool outputs is much more readable than the one from Vivado HLS. This makes it much easier for the designer to debug and modify the RTL.
DOI	10.1109/EWDTS.2016.7807644

View in source Özyeğin University Özyeğin University - Historical works, archives, and periodicals search engine

Özyeğin University

Using high-level synthesis for rapid design of video processing pipes

Author Güzel, Aydin Emre, Levent, Vecdi Emre, Tosun, Mustafa, Özkan, M. Akif, Akgun, T., Büyükaydın, D., Erbas, C., Uğurdağ, Hasan Fatih

Publication Date 2016

Publication Place - IEEE

Subject High-level synthesis, Vivado HLS, Video processing pipelines, Optical flow

Type Document

Language English

Digital Yes

Manuscript No

Library Özyeğin University

Library Asset ID 978-1-5090-0693-9

Record ID a6a8d24e-1735-40fb-b778-03bf3069b9e6

Library Location Electrical & Electronics Engineering

Date 2016

Notes Due to copyright restrictions, the access to the full text of this article is only available via subscription.

Sample Text In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has turned out to be pretty general-purpose except for the ability to handle cyclic inter-iteration dependencies. It also introduces some novel concepts to HLS, such as “pipelined multiplexers”. The synthesis results show that we can achieve better timing or better area results compared to Vivado HLS. Furthermore, the Verilog RTL our HLS tool outputs is much more readable than the one from Vivado HLS. This makes it much easier for the designer to debug and modify the RTL.

DOI 10.1109/EWDTS.2016.7807644